Electrical Characterization of High-k PMNT Thin Film Material

Book excerpt: This thesis presents the electrical characterization of high-k PMNT (lead magnesium niobate-lead titanate, Pb(Mg0:33Nb0:67)0:65Ti0:35O3) materials for MIM capacitor applications. In order to extract the dielectric properties of the PMNT material, a series of circular capacitors, transmission lines and square pads test structures were designed, fabricated and investigated. A set of guidelines that show the optimum dimensions in the design of coplanar dielectric characterization structures was obtained. A method for measuring the complex permittivity of dielectric material on a dielectric/metal stack was developed. The combination of C-V measurement and S-parameter measurement has been shown to be suitable for characterization of dielectric material on complex device cross-sections. Based on the results obtained, a design methodology for optimum test structure layout was achieved. Also, an efficient extraction approach was verified for the extraction the dielectric constant ({uF065}r) of insulator materials. The technique works by comparing the propagation constant extracted from S-parameter measurements and electromagnetic simulations. The extracted {uF065}r of the typical PMNT material was 950. De-embedding measurements were used to extract the resistance, inductance, capacitance and conductance per unit length of the devices studied. Systematic electrical and ferroelectric characterization of PMNT thin-films with different fabrication parameters was investigated. The PMNT thin-films were processed under different conditions including annealing at various temperatures. A significant high-k of 1115 (high capacitance density of 26 fF/cm2) for a PMNT MIM capacitor was achieved. In addition, small leakage current density of 2{u00D7}10-10 A/cm2 and low loss tangent of 0.0188 were also obtained. These results clearly showed that the PMNT MIM capacitors are very promising for both decoupling and more general RF and mixed-signal applications until the year 2020 according to ITRS, provided that the annealing temperatures can be further reduced to the 350oC range for compatibility with acceptable back-end processing temperature ranges.