Performance Directed Technology Mapping for LUT Based FPGAs

Book excerpt: In the second phase we re-inforce the results obtained in the first phase by a timing driven placement using a simulated annealing formulation. In this phase we minimize critical wirelengths and also control the non-critical wirelengths by assigning wirelengths required at each wire to achieve zero-slack. We then, proceed to achieve this goal via simulated annealing based placement. The outcome of the second phase is a set of placement and routing constraints which are then passed along with the mapped design of the first phase to the actual FPGA placement and route tools (Xilinx-apr [12]).