Physical Modeling and Analysis of Carrier Confinement and Transport in Silicon-on-insulator and Double-gate CMOS Devices and Circuits

Book excerpt: ABSTRACT: This dissertation mainly focuses on the development of a University of Florida generic process/physics-based compact model (UFDG) for complementary metal-oxide-semiconductor (CMOS) double-gate (DG) field-effect transistors (FETs), enabling predictive device/circuit simulations and analysis of extremely scaled DG CMOS. Further, updates and improvement of the University of Florida SOI (UFSOI) fully depleted (FD) and partially depleted (or non-fully depleted, NFD) MOSFET models are developed and applied to gain insight into the behavior of scaled SOI MOSFETs in integrated CMOS circuits. As the critical dimensions of MOSFETs shrink below 100 nm, Monte Carlo simulations of such devices show strong off-equilibrium transport effects such as velocity overshoot. A Boltzmann transport equation (BTE)-based analytical model for quasi-ballistic transport (i.e., velocity overshoot) was developed for scaled MOSFETs, and implemented in physics-based compact models (UFSOI/PD, UFSOI/FD, and UFDG), with verification and applications to extremely scaled devices. As the end of the Semiconductor Industry Association (SIA) roadmap is approached, DG MOSFETs, having thin Si-film bodies, will possibly constitute the mainstream CMOS technology due to their superior scalability.